Quantization of VLSI digital signal processing systems
Citation:
EURASIP Journal on Advances in Signal Processing
2012
2012:32
Quantization of VLSI Digital Signal Processing Systems
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Fixed-Point MAP Decoding of Channel Codes
This paper describes the fixed-point model of the maximum a posteriori (MAP) decoding algorithm of turbo and low-density parity-check (LDPC) codes, the most advanced channel codes adopted by modern communicati...
Citation: EURASIP Journal on Advances in Signal Processing 2011 2011:184635 -
Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design
High-level synthesis (HLS) currently seems to be an interesting process to reduce the design time substantially. HLS tools actually map algorithms to architectures. Conventional HLS techniques usually focus on...
Citation: EURASIP Journal on Advances in Signal Processing 2011 2011:927670 -
Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters
The coefficient values and number representations of digital FIR filters have significant impacts on the complexity of their VLSI realizations and thus on the system cost and performance. So, making a good tra...
Citation: EURASIP Journal on Advances in Signal Processing 2011 2011:357906 -
Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT
Using a specific input-restructuring sequence, a new VLSI algorithm and architecture have been derived for a high throughput memory-based systolic array VLSI implementation of a discrete cosine transform. The ...
Citation: EURASIP Journal on Advances in Signal Processing 2010 2011:639043 -
Sensitivity-Based Pole and Input-Output Errors of Linear Filters as Indicators of the Implementation Deterioration in Fixed-Point Context
Input-output or poles sensitivity is widely used to evaluate the resilience of a filter realization to coefficients quantization in an FWL implementation process. However, these measures do not exactly conside...
Citation: EURASIP Journal on Advances in Signal Processing 2010 2011:893760 -
Automatic IP Generation of FFT/IFFT Processors with Word-Length Optimization for MIMO-OFDM Systems
A systematic approach is presented for automatically generating variable-size FFT/IFFT soft intellectual property (IP) cores for MIMO-OFDM systems. The finite-precision effect in an FFT processor is first anal...
Citation: EURASIP Journal on Advances in Signal Processing 2010 2011:136319