Scheduling parity checks for increased throughput in early-termination, layered decoding of QC-LDPC codes on a stream processor
A stream processor is a power-efficient, high-level-language programmable option for embedded applications that are computation intensive and admit high levels of data parallelism. Many signal-processing algor...
EURASIP Journal on Wireless Communications and Networking 2012 2012:141
Published on: 12 April 2012