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Design and Architectures for Signal and Image Processing 2008

  1. Research

    An optimised twin precision multiplier for ASIC environment

    In this paper, we present the performance of twin precision technique in reduced computation modified booth (RCMB) multiplier to achieve double throughput, and an algorithm is proposed. Twin precision techniqu...

    Rosi Asirvatham and Seshasayanan Ramachandran

    EURASIP Journal on Advances in Signal Processing 2015 2015:18

    Published on: 4 March 2015

  2. Research Article

    High Speed 3D Tomography on CPU, GPU, and FPGA

    Back-projection (BP) is a costly computational step in tomography image reconstruction such as positron emission tomography (PET). To reduce the computation time, this paper presents a pipelined, prefetch, and...

    Nicolas GAC, Stéphane Mancini, Michel Desvignes and Dominique Houzet

    EURASIP Journal on Embedded Systems 2009 2008:930250

    Published on: 18 January 2009

  3. Research Article

    An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing

    A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a m...

    Dominique Ginhac, Jérôme Dubois, Michel Paindavoine and Barthélémy Heyrman

    EURASIP Journal on Embedded Systems 2009 2008:961315

    Published on: 18 January 2009

  4. Research Article

    Flexible Hardware-Based Stereo Matching

    To enable adaptive stereo vision for hardware-based embedded stereo vision systems, we propose a novel technique for implementing a flexible block size, disparity range, and frame rate. By reusing existing res...

    Kristian Ambrosch, Wilfried Kubinger, Martin Humenberger and Andreas Steininger

    EURASIP Journal on Embedded Systems 2009 2008:386059

    Published on: 18 January 2009

  5. Research Article

    An Evaluation of Dynamic Partial Reconfiguration for Signal and Image Processing in Professional Electronics Applications

    Signal and image processing applications require a lot of computing resources. For low-volume applications like in professional electronics applications, FPGA are used in combination with DSP and GPP in order ...

    Philippe Manet, Daniel Maufroid, Leonardo Tosi, Gregory Gailliard, Olivier Mulertt, Marco Di Ciano, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba, Pol Cuvelier, Bertrand Rousseau and Paul Gelineau

    EURASIP Journal on Embedded Systems 2009 2008:367860

    Published on: 11 January 2009

  6. Research Article

    Design of a Real-Time Face Detection Parallel Architecture Using High-Level Synthesis

    We describe a High-Level Synthesis implementation of a parallel architecture for face detection. The chosen face detection method is the well-known Convolutional Face Finder (CFF) algorithm, which consists of ...

    Nicolas Farrugia, Franck Mamalet, Sébastien Roux, Fan Yang and Michel Paindavoine

    EURASIP Journal on Embedded Systems 2008 2008:938256

    Published on: 24 December 2008

  7. Research Article

    A Platform for the Development and the Validation of HW IP Components Starting from Reference Software Specifications

    Signal processing algorithms become more and more efficient as a result of the developments of new standards. It is particularly true in the field video compression. However, at each improvement in efficiency ...

    Christophe Lucarz, Marco Mattavelli and Julien Dubois

    EURASIP Journal on Embedded Systems 2008 2008:685139

    Published on: 25 November 2008

  8. Research Article

    Smart Camera Based on Embedded HW/SW Coprocessor

    This paper describes an image acquisition and a processing system based on a new coprocessor architecture designed for CMOS sensor imaging. The system exploits the full potential CMOS selective access imaging ...

    Romuald Mosqueron, Julien Dubois, Marco Mattavelli and David Mauvilet

    EURASIP Journal on Embedded Systems 2008 2008:597872

    Published on: 26 October 2008

  9. Research Article

    A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis

    This paper presents a metric-based approach for estimating the hardware implementation effort (in terms of time) for an application in relation to the number of linear-independent paths of its algorithms. We e...

    Rasmus Abildgren, Jean-Philippe Diguet, Pierre Bomel, Guy Gogniat, Peter Koch and Yannick Le Moullec

    EURASIP Journal on Embedded Systems 2008 2008:280347

    Published on: 26 October 2008

  10. Research Article

    Accuracy Constraint Determination in Fixed-Point System Design

    Most of digital signal processing applications are specified and designed with floatingpoint arithmetic but are finally implemented using fixed-point architectures. Thus, the design flow requires a floating-po...

    D Menard, R Serizel, R Rocher and O Sentieys

    EURASIP Journal on Embedded Systems 2008 2008:242584

    Published on: 13 October 2008

  11. Research Article

    Using High-Level RTOS Models for HW/SW Embedded Architecture Exploration: Case Study on Mobile Robotic Vision

    We are interested in the design of a system-on-chip implementing the vision system of a mobile robot. Following a biologically inspired approach, this vision architecture belongs to a larger sensorimotor loop....

    François Verdier, Benoît Miramond, Mickaël Maillard, Emmanuel Huck and Thomas Lefebvre

    EURASIP Journal on Embedded Systems 2008 2008:349465

    Published on: 4 August 2008

  12. Research Article

    Multiple Word-Length High-Level Synthesis

    Digital signal processing (DSP) applications are nowadays widely used and their complexity is ever growing. The design of dedicated hardware accelerators is thus still needed in system-on-chip and embedded sys...

    Philippe Coussy, Ghizlane Lhairech-Lebreton and Dominique Heller

    EURASIP Journal on Embedded Systems 2008 2008:916867

    Published on: 29 July 2008