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Design Methods for DSP Systems

  1. Research Article

    A Fully Automated Environment for Verification of Virtual Prototypes

    The extremely dynamic and competitive nature of the wireless communication systems market demands ever shorter times to market for new products. Virtual prototyping has emerged as one of the most promising tec...

    P Belanović, B Knerr, M Holzer and M Rupp

    EURASIP Journal on Advances in Signal Processing 2006 2006:032408

    Published on: 18 May 2006

  2. Research Article

    Multiple-Clock-Cycle Architecture for the VLSI Design of a System for Time-Frequency Analysis

    Multiple-clock-cycle implementation (MCI) of a flexible system for time-frequency (TF) signal analysis is presented. Some very important and frequently used time-frequency distributions (TFDs) can be realized ...

    Veselin N. Ivanović, Radovan Stojanović and L Jubivša Stanković

    EURASIP Journal on Advances in Signal Processing 2006 2006:060613

    Published on: 12 March 2006

  3. Research Article

    A New Pipelined Systolic Array-Based Architecture for Matrix Inversion in FPGAs with Kalman Filter Case Study

    A new pipelined systolic array-based (PSA) architecture for matrix inversion is proposed. The pipelined systolic array (PSA) architecture is suitable for FPGA implementations as it efficiently uses available r...

    Abbas Bigdeli, Morteza Biglari-Abhari, Zoran Salcic and Yat Tin Lai

    EURASIP Journal on Advances in Signal Processing 2006 2006:089186

    Published on: 8 March 2006

  4. Research Article

    FPGA Implementation of an MUD Based on Cascade Filters for a WCDMA System

    The VLSI architecture targeted on FPGAs of a multiuser detector based on a cascade of adaptive filters for asynchronous WCDMA systems is presented. The algorithm is briefly described. This paper focuses mainly...

    Quoc-Thai Ho, Daniel Massicotte and Adel-Omar Dahmane

    EURASIP Journal on Advances in Signal Processing 2006 2006:052919

    Published on: 8 March 2006

  5. Research Article

    Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions

    This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce application-specific customized instructions and highly parallel combinational ha...

    Raymond R. Hoare, Alex K. Jones, Dara Kusic, Joshua Fazekas, John Foster, Shenchih Tung and Michael McCloud

    EURASIP Journal on Advances in Signal Processing 2006 2006:046472

    Published on: 2 March 2006

  6. Research Article

    Optimum Wordlength Search Using Sensitivity Information

    Many digital signal processing algorithms are first developed in floating point and later converted into fixed point for digital hardware implementation. During this conversion, more than 50% of the design tim...

    Kyungtae Han and Brian L. Evans

    EURASIP Journal on Advances in Signal Processing 2006 2006:092849

    Published on: 2 March 2006

  7. Research Article

    3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems

    This paper introduces a novel architecture for next-generation adaptive computing systems, which we term 3D-SoftChip. The 3D-SoftChip is a 3-dimensional (3D) vertically integrated adaptive computing system com...

    Chul Kim, Alex Rassau, Stefan Lachowicz, Mike Myung-Ok Lee and Kamran Eshraghian

    EURASIP Journal on Advances in Signal Processing 2006 2006:075032

    Published on: 20 February 2006

  8. Research Article

    Rapid Prototyping for Heterogeneous Multicomponent Systems: An MPEG-4 Stream over a UMTS Communication Link

    Future generations of mobile phones, including advanced video and digital communication layers, represent a great challenge in terms of real-time embedded systems. Programmable multicomponent architectures can...

    M. Raulet, F. Urban, J.-F. Nezan, C. Moy, O. Deforges and Y. Sorel

    EURASIP Journal on Advances in Signal Processing 2006 2006:064369

    Published on: 16 February 2006

  9. Research Article

    Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL) architecture, starting from a Matlab functional model descri...

    Nacer-Eddine Zergainoh, Ludovic Tambour, Pascal Urard and Ahmed Amine Jerraya

    EURASIP Journal on Advances in Signal Processing 2006 2006:028636

    Published on: 30 January 2006

  10. Research Article

    Floating-to-Fixed-Point Conversion for Digital Signal Processors

    Digital signal processing applications are specified with floating-point data types but they are usually implemented in embedded systems with fixed-point arithmetic to minimise cost and power consumption. Thus...

    Daniel Menard, Daniel Chillet and Olivier Sentieys

    EURASIP Journal on Advances in Signal Processing 2006 2006:096421

    Published on: 6 January 2006