Algorithm and implementation aspects of channel codes and iterative receivers

Scheduling parity checks for increased throughput in early-termination, layered decoding of QC-LDPC codes on a stream processor

A stream processor is a power-efficient, high-level-language programmable option for embedded applications that are computation intensive and admit high levels of data parallelism. Many signal-processing algor...

Authors: JaWone A Kennedy and Daniel L Noneaker

Citation: EURASIP Journal on Wireless Communications and Networking 2012 2012:141

Content type: Research Published on: 12 April 2012
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Low complexity frequency domain hybrid-ARQ chase combining for broadband MIMO CDMA systems

In this article, we investigate efficient minimum mean square error (MMSE) frequency domain equalization (FDE)-based iterative (turbo) packet combining for cyclic prefix (CP)-CDMA MIMO with Chase-type ARQ. We ...

Authors: Houda Chafnaji, Tarik Ait-Idir, Samir Saoudi and Athanasios V Vasilakos

Citation: EURASIP Journal on Wireless Communications and Networking 2012 2012:134

Content type: Research Published on: 5 April 2012
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