Rapid Prototyping of DSP Systems
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Citation: EURASIP Journal on Advances in Signal Processing 2003 2003:865381
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A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs
Area-efficient peak-constrained least-squares (PCLS) bit-serial finite impulse response (FIR) filter implementations can be rapidly prototyped in field programmable gate arrays (FPGA) with the methodology pres...
Citation: EURASIP Journal on Advances in Signal Processing 2003 2003:804527 -
A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems
We provide a methodology used for the temporal partitioning of the data-path part of an algorithm for a reconfigurable embedded system. Temporal partitioning of applications for reconfigurable computing system...
Citation: EURASIP Journal on Advances in Signal Processing 2003 2003:743410 -
Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems
We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems ...
Citation: EURASIP Journal on Advances in Signal Processing 2003 2003:720828 -
Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations
A method for the rapid design of field programmable gate array (FPGA)-based discrete cosine transform (DCT) approximations is presented that can be used to control the coding gain, mean square error (MSE), qua...
Citation: EURASIP Journal on Advances in Signal Processing 2003 2003:687253 -
Memory-Optimized Software Synthesis from Dataflow Program Graphs with Large Size Data Samples
In multimedia and graphics applications, data samples of nonprimitive type require significant amount of buffer memory. This paper addresses the problem of minimizing the buffer memory requirement for such app...
Citation: EURASIP Journal on Advances in Signal Processing 2003 2003:650391 -
Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware
The implementation of large linear control systems requires a high amount of digital signal processing. Here, we show that reconfigurable hardware allows the design of fast yet flexible control systems. After ...
Citation: EURASIP Journal on Advances in Signal Processing 2003 2003:504157 -
How Rapid is Rapid Prototyping? Analysis of ESPADON Programme Results
New methodologies, engineering processes, and support environments are beginning to emerge for embedded signal processing systems. The main objectives are to enable defence industry to field state-of-the-art p...
Citation: EURASIP Journal on Advances in Signal Processing 2003 2003:349675 -
Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications
This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploratio...
Citation: EURASIP Journal on Advances in Signal Processing 2003 2003:205943 -
A Rapid Prototyping Environment for Wireless Communication Embedded Systems
This paper introduces a rapid prototyping methodology which overcomes important barriers in the design and implementation of digital signal processing (DSP) algorithms and systems on embedded hardware platform...
Citation: EURASIP Journal on Advances in Signal Processing 2003 2003:187410 -
An FPGA Implementation of
-Regular Low-Density Parity-Check Code Decoder
Because of their excellent error-correcting performance, low-density parity-check (LDPC) codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder ha...
Citation: EURASIP Journal on Advances in Signal Processing 2003 2003:169168