Time-domain equalization is crucial in reducing channel state dimension in maximum likelihood sequence estimation and intercarrier and intersymbol interference in multicarrier systems. A time-domain equalizer ...
We propose a new signal security system and its VLSI architecture for real-time multimedia data transmission applications. We first define two bit-circulation functions for one-dimensional binary array transfo...
A novel design and implementation of an online reconfigurable Viterbi decoder is proposed, based on an area-efficient add-compare-select (ACS) architecture, in which the constraint length and traceback depth c...
The goal of this paper is to reduce the decoding complexity of space-time block turbo-coded system with low performance degradation. Two block turbo-coded systems with antenna diversity are considered. These i...
In mobile positioning, it is very important to estimate correctly the delay between the transmitter and the receiver. When the receiver is in line-of-sight (LOS) condition with the transmitter, the computation...
The technique of orthogonal frequency division multiplexing (OFDM) is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless commun...
We propose an area-efficient high-speed interleaved Viterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional c...
This paper presents new application-specific digital signal processor (ASDSP) instructions and their hardware accelerator to efficiently implement Reed-Solomon (RS) encoding and decoding, which is one of the m...
This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility...