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Design and Architectures for Signal and Image Processing 2008

  1. Indoor positioning based on wireless local area network (WLAN) signals is often enhanced using pedestrian dead reckoning (PDR) based on an inertial measurement unit. The state evolution model in PDR is usually...

    Authors: Matti Raitoharju, Henri Nurminen and Robert Piché
    Citation: EURASIP Journal on Advances in Signal Processing 2015 2015:33
  2. In this paper, we present the performance of twin precision technique in reduced computation modified booth (RCMB) multiplier to achieve double throughput, and an algorithm is proposed. Twin precision techniqu...

    Authors: Rosi Asirvatham and Seshasayanan Ramachandran
    Citation: EURASIP Journal on Advances in Signal Processing 2015 2015:18
  3. The objective of this paper is to compare the performance of singular value decomposition (SVD), expectation maximization (EM), and modified expectation maximization (MEM) as the postclassifiers for classifica...

    Authors: Rajaguru Harikumar and Thangavel Vijayakumar
    Citation: EURASIP Journal on Advances in Signal Processing 2014 2014:59
  4. A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a m...

    Authors: Dominique Ginhac, Jérôme Dubois, Michel Paindavoine and Barthélémy Heyrman
    Citation: EURASIP Journal on Embedded Systems 2009 2008:961315
  5. Back-projection (BP) is a costly computational step in tomography image reconstruction such as positron emission tomography (PET). To reduce the computation time, this paper presents a pipelined, prefetch, and...

    Authors: Nicolas GAC, Stéphane Mancini, Michel Desvignes and Dominique Houzet
    Citation: EURASIP Journal on Embedded Systems 2009 2008:930250
  6. To enable adaptive stereo vision for hardware-based embedded stereo vision systems, we propose a novel technique for implementing a flexible block size, disparity range, and frame rate. By reusing existing res...

    Authors: Kristian Ambrosch, Wilfried Kubinger, Martin Humenberger and Andreas Steininger
    Citation: EURASIP Journal on Embedded Systems 2009 2008:386059
  7. Signal and image processing applications require a lot of computing resources. For low-volume applications like in professional electronics applications, FPGA are used in combination with DSP and GPP in order ...

    Authors: Philippe Manet, Daniel Maufroid, Leonardo Tosi, Gregory Gailliard, Olivier Mulertt, Marco Di Ciano, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Raffaele Liberati, Vincenzo La Barba, Pol Cuvelier, Bertrand Rousseau and Paul Gelineau
    Citation: EURASIP Journal on Embedded Systems 2009 2008:367860
  8. We describe a High-Level Synthesis implementation of a parallel architecture for face detection. The chosen face detection method is the well-known Convolutional Face Finder (CFF) algorithm, which consists of ...

    Authors: Nicolas Farrugia, Franck Mamalet, Sébastien Roux, Fan Yang and Michel Paindavoine
    Citation: EURASIP Journal on Embedded Systems 2008 2008:938256
  9. Signal processing algorithms become more and more efficient as a result of the developments of new standards. It is particularly true in the field video compression. However, at each improvement in efficiency ...

    Authors: Christophe Lucarz, Marco Mattavelli and Julien Dubois
    Citation: EURASIP Journal on Embedded Systems 2008 2008:685139
  10. This paper describes an image acquisition and a processing system based on a new coprocessor architecture designed for CMOS sensor imaging. The system exploits the full potential CMOS selective access imaging ...

    Authors: Romuald Mosqueron, Julien Dubois, Marco Mattavelli and David Mauvilet
    Citation: EURASIP Journal on Embedded Systems 2008 2008:597872
  11. This paper presents a metric-based approach for estimating the hardware implementation effort (in terms of time) for an application in relation to the number of linear-independent paths of its algorithms. We e...

    Authors: Rasmus Abildgren, Jean-Philippe Diguet, Pierre Bomel, Guy Gogniat, Peter Koch and Yannick Le Moullec
    Citation: EURASIP Journal on Embedded Systems 2008 2008:280347
  12. Most of digital signal processing applications are specified and designed with floatingpoint arithmetic but are finally implemented using fixed-point architectures. Thus, the design flow requires a floating-po...

    Authors: D Menard, R Serizel, R Rocher and O Sentieys
    Citation: EURASIP Journal on Embedded Systems 2008 2008:242584
  13. We are interested in the design of a system-on-chip implementing the vision system of a mobile robot. Following a biologically inspired approach, this vision architecture belongs to a larger sensorimotor loop....

    Authors: François Verdier, Benoît Miramond, Mickaël Maillard, Emmanuel Huck and Thomas Lefebvre
    Citation: EURASIP Journal on Embedded Systems 2008 2008:349465
  14. Digital signal processing (DSP) applications are nowadays widely used and their complexity is ever growing. The design of dedicated hardware accelerators is thus still needed in system-on-chip and embedded sys...

    Authors: Philippe Coussy, Ghizlane Lhairech-Lebreton and Dominique Heller
    Citation: EURASIP Journal on Embedded Systems 2008 2008:916867