Skip to main content

Design and Architectures for Signal and Image Processing 2009

  1. This paper presents the design of an FPGA-based multiprocessor-system-on-chip (MPSoC) architecture optimized for Multiple Target Tracking (MTT) in automotive applications. An MTT system uses an automotive rada...

    Authors: Jehangir Khan, Smail Niar, MazenAR Saghir, Yassin El-Hillali and Atika Rivenq-Menhaj
    Citation: EURASIP Journal on Embedded Systems 2010 2009:175043
  2. This is a comment article on the publication "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes" Rovini et al. (2009). We mention that there has been similar work reported in th...

    Authors: KiranK Gunnam, GwanS Choi and MarkB Yeary
    Citation: EURASIP Journal on Embedded Systems 2010 2009:704174
  3. This is a reply to the comments by Gunnam et al. "Comments on 'Techniques and architectures for hazard-free semi-parallel decoding of LDPC codes'", EURASIP Journal on Embedded Systems, vol. 2009, Article ID 70417...

    Authors: Massimo Rovini, Giuseppe Gentile, Francesco Rossi and Luca Fanucci
    Citation: EURASIP Journal on Embedded Systems 2010 2009:635895
  4. The aim of this paper is to present an adaptable Fat Tree NoC architecture for Field Programmable Gate Array (FPGA) designed for image analysis applications. Traditional Network on Chip (NoC) is not optimal fo...

    Authors: Linlin Zhang, Virginie Fresse, Mohammed Khalid, Dominique Houzet and Anne-Claire Legrand
    Citation: EURASIP Journal on Embedded Systems 2009 2009:542035
  5. This paper presents a very low-memory wavelet compression architecture for implementation in severely constrained hardware environments such as wireless sensor networks (WSNs). The approach employs a strip-bas...

    Authors: LiWern Chew, WaiChong Chia, Li-minn Ang and KahPhooi Seng
    Citation: EURASIP Journal on Embedded Systems 2009 2009:479281
  6. Embedded real-time applications in communication systems have significant timing constraints, thus requiring multiple computation units. Manually exploring the potential parallelism of an application deployed ...

    Authors: Maxime Pelcat, Jonathan Piat, Matthieu Wipliez, Slaheddine Aridhi and Jean-François Nezan
    Citation: EURASIP Journal on Embedded Systems 2009 2009:598529
  7. Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the lo...

    Authors: MuhammadYasir Qadri and KlausD McDonald-Maier
    Citation: EURASIP Journal on Embedded Systems 2009 2009:725438
  8. Since few years, the gastroenterologic examinations could have been realised by wireless video capsules. Although the images make it possible to analyse some diseases, the diagnosis could be improved by the us...

    Authors: Anthony Kolar, Olivier Romain, Jade Ayoub, David Faura, Sylvain Viateur, Bertrand Granado and Tarik Graba
    Citation: EURASIP Journal on Embedded Systems 2009 2009:716317
  9. This paper presents an efficient dynamic and run-time Hardware/Software scheduling approach. This scheduling heuristic consists in mapping online the different tasks of a highly dynamic application in such a w...

    Authors: Fakhreddine Ghaffari, Benoit Miramond and François Verdier
    Citation: EURASIP Journal on Embedded Systems 2009 2009:976296
  10. This paper describes a hardware architecture to implement the watershed algorithm using rainfall simulation. The speed of the architecture is increased by utilizing a multiple memory bank approach to allow par...

    Authors: LeeSeng Yeong, ChristopherWingHong Ngau, Li-Minn Ang and KahPhooi Seng
    Citation: EURASIP Journal on Embedded Systems 2009 2009:318654
  11. Wavelet-based automated global image registration (WAGIR) is fundamental for most remote sensing image processing algorithms and extremely computation-intensive. With more and more algorithms migrating from gr...

    Authors: Baofeng Li, Yong Dou, Haifang Zhou and Xingming Zhou
    Citation: EURASIP Journal on Embedded Systems 2009 2009:162078
  12. H.264 delivers the streaming video in high quality for various applications. The coding tools involved in H.264, however, make its video codec implementation very complicated, raising the need for algorithm op...

    Authors: Yifeng Qiu and Wael Badawy
    Citation: EURASIP Journal on Embedded Systems 2009 2009:105979
  13. The layered decoding algorithm has recently been proposed as an efficient means for the decoding of low-density parity-check (LDPC) codes, thanks to the remarkable improvement in the convergence speed (2x) of ...

    Authors: Massimo Rovini, Giuseppe Gentile, Francesco Rossi and Luca Fanucci
    Citation: EURASIP Journal on Embedded Systems 2009 2009:723465
  14. This article presents an efficient method to capture abstract performance model of streaming data real-time embedded systems (RTESs). Unified Modeling Language version 2 (UML2) is used for the performance mode...

    Authors: Tero Arpinen, Erno Salminen, Timo D Hämäläinen and Marko Hännikäinen
    Citation: EURASIP Journal on Embedded Systems 2009 2009:826296
  15. We describe a multicore Software-Defined Radio (SDR) architecture for Global Navigation Satellite System (GNSS) receiver implementation. A GNSS receiver picks up very low power signals from multiple satellites...

    Authors: Heikki Hurskainen, Jussi Raasakka, Tapani Ahonen and Jari Nurmi
    Citation: EURASIP Journal on Embedded Systems 2009 2009:543720
  16. The HESS project has been running successfully for seven years. In order to take into account the sensitivity increase of the entire project in its second phase, a new trigger scheme is proposed. This trigger ...

    Authors: Sonia Khatchadourian, Jean-Christophe Prévotet and Lounis Kessal
    Citation: EURASIP Journal on Embedded Systems 2009 2009:737689