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Dynamically Reconfigurable Architectures

  1. Content type: Research Article

    Digital film processing is characterized by a resolution of at least 2 K (2048×1536 pixels per frame at 30 bit/pixel and 24 pictures/s, data rate of 2.2 Gbit/s); higher resolutions of 4 K (8.8 Gbit/s) and even...

    Authors: Sven Heithecker, Amilcar do Carmo Lucas and Rolf Ernst

    Citation: EURASIP Journal on Embedded Systems 2007 2007:085318

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  2. Content type: Research Article

    We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applica...

    Authors: Gerard JM Smit, André BJ Kokkeler, Pascal T Wolkotte, Philip KF Hölzenspies, Marcel D van de Burgwal and Paul M Heysters

    Citation: EURASIP Journal on Embedded Systems 2007 2007:078082

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  3. Content type: Research Article

    We show how the limited electrical power and FPGA compute resources available in a swarm of small UAVs can be shared by moving FPGA tasks from one UAV to another. A software and hardware infrastructure that su...

    Authors: David Kearney and Mark Jasiunas

    Citation: EURASIP Journal on Embedded Systems 2007 2007:048521

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  4. Content type: Research Article

    Free-space optical interconnects (FSOIs) are widely seen as a potential solution to current and future bandwidth bottlenecks for parallel processors. In this paper, an FSOI system called optical highway (OH) i...

    Authors: Rafael Gil-Otero, Theodore Lim and John F Snowdon

    Citation: EURASIP Journal on Embedded Systems 2007 2007:067603

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  5. Content type: Research Article

    For certain applications, custom computational hardware created using field programmable gate arrays (FPGAs) can produce significant performance improvements over processors, leading some in academia and indus...

    Authors: Stephen Craven and Peter Athanas

    Citation: EURASIP Journal on Embedded Systems 2007 2007:093652

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